DSPIC30F4011-30I/ML【PDF 30/238 页】IC DSPIC MCU/DSP 48K 44QFN

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Sheet目录1917

26页 27页 28页 29页 [30页]31页 32页 33页 34页

2010 Microchip Technology Inc.

DS70135G-page 125

dsPIC30F4011/4012

18.5.2

FRAMING ERROR (FERR)

The FERR bit (UxSTA<2>) is set if a ‘0’ is detected

instead of a Stop bit. If two Stop bits are selected, both

Stop bits must be ‘1’, otherwise FERR will be set. The

read-only FERR bit is buffered along with the received

data; it is cleared on any Reset.

18.5.3

PARITY ERROR (PERR)

The PERR bit (UxSTA<3>) is set if the parity of the

received word is incorrect. This error bit is applicable

only if a Parity mode (odd or even) is selected. The

read-only PERR bit is buffered along with the received

data bytes; it is cleared on any Reset.

18.5.4

IDLE STATUS

When the receiver is active (i.e., between the initial

detection of the Start bit and the completion of the Stop

bit), the RIDLE bit (UxSTA<4>) is ‘0’. Between the

completion of the Stop bit and detection of the next

Start bit, the RIDLE bit is ‘1’, indicating that the UART

is Idle.

18.5.5

RECEIVE BREAK

The receiver will count and expect a certain number

of bit times based on the values programmed in

the

PDSEL<1:0>

(UxMODE<2:1>)

and

STSEL

(UxMODE<0>) bits.

If the Break is longer than 13 bit times, the reception is

considered complete after the number of bit times

specified by PDSEL and STSEL. The URXDA bit is

set, FERR is set, zeros are loaded into the receive

FIFO, interrupts are generated, if appropriate and the

RIDLE bit is set.

When the module receives a long Break signal and the

receiver has detected the Start bit, the data bits and

the invalid Stop bit (which sets the FERR), the receiver

must wait for a valid Stop bit before looking for the next

Start bit. It cannot assume that the Break condition on

the line is the next Start bit.

Break is regarded as a character containing all ‘0’s,

with the FERR bit set. The Break character is loaded

into the buffer. No further reception can occur until a

Stop bit is received. Note that RIDLE goes high when

the Stop bit has not been received yet.

18.6

Address Detect Mode

Setting the ADDEN bit (UxSTA<5>) enables this

special mode in which a 9th bit (URX8) value of ‘1’

identifies the received word as an address, rather than

data. This mode is only applicable for 9-bit data

communication. The URXISELx control bit does not

have any impact on interrupt generation in this mode,

since an interrupt (if enabled) will be generated every

time the received word has the 9th bit set.

18.7

Loopback Mode

Setting the LPBACK bit enables this special mode in

which the UxTX pin is internally connected to the UxRX

pin. When configured for the Loopback mode, the

UxRX pin is disconnected from the internal UART

receive logic. However, the UxTX pin still functions as

in a normal operation.

To select this mode:

Configure UART for desired mode of operation.

Set LPBACK = 1 to enable Loopback mode.

Enable transmission as defined in Section 18.3

“Transmitting Data”.

18.8

Baud Rate Generator

The UART has a 16-bit Baud Rate Generator to allow

maximum flexibility in baud rate generation. The Baud

Rate Generator register (UxBRG) is readable and

writable. The baud rate is computed as follows:

BRG = 16-bit value held in UxBRG register

(0 through 65535)

FCY

= Instruction Clock Rate (1/TCY)

The baud rate is given by Equation 18-1.

EQUATION 18-1:

BAUD RATE

Therefore, maximum baud rate possible is:

FCY/16 (if BRG = 0),

and the minimum baud rate possible is:

FCY/(16 * 65536).

With a full, 16-bit Baud Rate Generator, at 30 MIPS

operation, the minimum baud rate achievable is

28.5 bps.

Baud Rate = FCY/(16 * (BRG + 1))

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